Last update: August 2026
Building larger quantum computers is not simply a matter of adding more qubits. As systems grow, limited connectivity, qubit movement, communication between modules, control constraints, and architectural heterogeneity increasingly determine how efficiently computations can be executed.
In my group, we investigate scalable quantum computer architectures, with a particular focus on modular and multi-core systems, spin-qubit processors, and hardware-software co-design. We treat architecture as a design space: Which architectural choices are beneficial for which workloads, and how should hardware and software evolve together?
Many current quantum computers are designed and programmed as if all qubits belonged to a single tightly connected processor. This becomes increasingly difficult to maintain as systems scale.
One direction of our work therefore explores modular and multi-core quantum architectures, in which computation is distributed across several interconnected cores or modules. Such systems introduce new questions about placement, communication, and resource management. Which operations should be assigned to which core? How much communication is required between modules? Which circuit structures fit a given topology? And when does communication become the dominant bottleneck?
We study these questions by characterizing quantum circuits and their communication requirements and relating them to architectural properties. This allows us to quantify the trade-offs that arise when moving from relatively small processors toward larger distributed systems.
There is no universally optimal quantum architecture. A design that performs well for one class of algorithms may be inefficient for another, while hardware choices that appear attractive in isolation can create substantial compilation overhead.
We therefore study hardware and software together. This includes detailed work on spin-qubit architectures, where physical constraints lead to characteristic connectivity, movement, and control requirements. Compiler information helps us evaluate these architectural choices under realistic workloads and quantify their consequences for execution.
A second direction is automated design-space exploration. We develop methods for systematically exploring architectural design alternatives and their trade-offs. This can involve processor organization, connectivity, communication mechanisms, and lower-level choices such as quantum gate sets.
Architectural models, compiler information, workload characteristics, and optimization methods provide the basis for systematic and quantitatively grounded design decisions.
A scalable architecture is useful only if the rest of the system can make effective use of it.
Compilation exposes communication and connectivity bottlenecks. Error-correction schemes introduce additional resource and control requirements. Applications determine which architectural capabilities are important in practice.
We therefore evaluate architectural ideas through their consequences for compilation and execution. Compiler and application results, in turn, provide feedback on how future processors should be designed.
This interaction between workloads, software, and hardware is central to our approach to full-stack quantum system design.
YAQQ: yet another quantum quantizer – design space exploration of quantum gate sets using novelty search. New Journal of Physics, 2026.
Stacking the odds: full-stack quantum system design space exploration. EPJ Quantum Technology, 2025.
Near-term spin-qubit architecture design via multipartite maximally entangled states. PRX Quantum, 2025.
ArtA: automating Design Space Exploration of spin-qubit architectures. Quantum Information Processing, 2025.
Characterizing the inter-core qubit traffic in large-scale quantum modular architectures. IEEE Access, 2025.
Profiling quantum circuits for their efficient execution on single- and multi-core architectures. Quantum Science and Technology, 2025.
YAQQ: Software for design-space exploration of quantum gate sets and quantum instruction sets, supporting hardware-software co-design across different processor assumptions.
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